1. Field of the Invention
The present invention relates to techniques for forming silicon MOSFET devices having spacers. More particularly, the present invention relates to techniques for forming semiconductor devices having reduced overlapped capacitance between gate and source/drain regions in MOSFET devices.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Layers are typically either grown (for example, thermal oxidation of silicon to grow a silicon dioxide dielectric layer) or deposited by a variety of techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), including evaporation and sputtering. Patterning, is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
Semiconductor device sizes have decreased dramatically over the years. The downsizing of the devices has resulted in increased performance. In order to accommodate sub-micron IC feature sizes, various technologies have been developed and applied including thinner gate dielectrics and smaller gate dimensions. Each of these trends requires the solution of problems created by the miniaturization. For example, the investigation of exotic materials for the gate dielectric layers have resulted from the need to avoid problems such as tunneling inherent in thinner dielectrics. These new materials are difficult to manufacture. Moreover, severe problems, such as increased junction capacitance, arise from the shrinkage of junction depth for source/drain junctions into the sub 1000 Angstrom range.
Generally, the device performance is inversely proportional to the RC constant of the device, where R is the resistance of the gate and C is the intrinsic capacitance of the device. The capacitance is proportional to the dielectric constant and the area of the conductors but inversely proportional to the separation distance between the conductors. Thus, as the device dimensions decrease, so does the capacitance, resulting in faster device speeds.
As illustrated in FIG. 1, the intrinsic capacitance of an MOSFET device is a combination the junction capacitance (Cj) 102, gate capacitance (Cg) 104, overlapped capacitance in the drain region (Cop-d) 106, overlapped capacitance in the source region (Cop-s) 108, and gate to substrate capacitance (Cgb) 110. The overlapped capacitance is generally described as the capacitance arising from the overlap of the gate with the source or drain regions. Although device scaling increases device performance, further performance improvement can be obtained from reductions in overlapped capacitance. The more a device is scaled, the more intrinsic capacitance plays an important role in the device performance. In particular, since the overlap capacitance is not scaled with device size, its importance in device performance is critical. Thus, the benefit from the reduction of overlap capacitance is more obvious and dramatic.
Accordingly, it is desirable to increase the device performance without undertaking major processing equipment expenditures. It is desirable to increase the device performance by reducing the capacitance of the device, without requiring reduction of device dimensions.
To achieve the foregoing, the present invention provides a process for forming a Silicon MOSFET device having a reduced overlapped capacitance. The present invention exploits the fact that device performance may be increased by reducing the capacitance of the device without shrinking the device gate dimensions. In particular, a lower overlapped capacitance is obtained by forming a composite spacer. Reduced capacitance is obtained using a low dielectric constant material formed on an oxide or other isolation layer.
In one aspect, the invention provides a method of forming a semiconductor device having reduced overlapped capacitance. A silicon dioxide (SiO2) layer or other spacer isolation layer is deposited after etching of the gate. A low dielectric constant spacer material is deposited after deposition of the oxide layer. The layers are then etched anisotropically using an etch chemical selective to the low k spacer material and non selective to the isolation layer to form spacers having reduced overlapped capacitance.
In another aspect, the low k spacer material comprises silicon carbide and the isolation layer comprises silicon dioxide. The thickness of the spacer (SiO2) isolation layer preferably is in the range from 50 to 300 xc3x85, and more preferably 100 xc3x85. The thickness of the SiC low k dielectric spacer material layer is preferably between about 500 to 1500 xc3x85 and more preferably 1000 xc3x85.
In yet another aspect, the low k spacer material comprises silicon oxycarbide and the spacer isolation layer comprises silicon dioxide. The thickness of the spacer (SiO2) isolation layer preferably is in the range from 50 to 300 xc3x85, and more preferably 100 xc3x85. The thickness of the silicon oxycarbide low k spacer material layer is preferably between about 300 to 1200 xc3x85 and more preferably 800 xc3x85.